Defensa de tesi de Quang Vinh Ngo
Defensa de tesi de Quang Vinh Ngoz el pròxim 20 de juny a les 11. Sala de Graus de l’Escola d’Enginyeria – Edifici Q.
Doctorand: Quang Vinh Ngo.
Títol: Reconfigurable HOG/SVM Implementations for Pedestrian Detection.
Directors: David Castells Rufas, Jordi Carrabina Bordoll.
Data i hora lectura: 20/06/2022 – 11h.
Lloc lectura: Sala de Graus de l’Escola d’Enginyeria – Edifici Q.
Programa de Doctorat: Enginyeria Electrònica i de Telecomunicació.
Departament on està inscrita la tesi: Departament de Microelectrònica i Sistemes Electrònics.
Pedestrian detection is one of the most safety-critical applications in autonomous cars. The requirement of this application is not only accuracy but also speed and energy efficiency. In the literature, there are two main approaches to solve the problem: deep neural network based algorithms, that achieve high accuracy yet require large amount of computing resource and power; and handcrafted features based classifications, more suitable for embedded platforms with limited amount of computing and memory resources.
Embedded platforms implemented using FPGAs and ASICs consume less power than GPU/CPU based systems to achieve similar results. On the other side, in terms of energy efficiency, GPUs is 10 times better than FPGAs in running CNN-based applications. However, FPGA-based implementations with low-level optimization techniques can beat GPU-based ones. Compared to ASICs, the advantage of FPGA device is that it is their re-configurability for later updates and time-to-market.
This thesis presents the implementation of pedestrian detection systems on FPGAs using Histogram of Gradient feature extractor and SVM classifier. First, the pipeline of the algorithm is implemented in Verilog HDL to achieve a high-throughput and low power consumption system. Second, the same algorithm is realized using OpenCL programming model, a high-level synthesis approach. To compare to the state-of-the-art, since different implementations have different working frequencies and input image resolution, I calculate the number of pixels per clock cycle for fair comparison. The implementation in this thesis achieves second to the best with 0,068 pixels per clock even though it uses equal or less FPGA resources than the rest. The system consumes the least power at only 9 W. In terms of energy efficiency, our result achieves the third best at 1,22 FPS per Watt. However, the working frequency of this design is only half as high as the frequencies of the other implementations. If the pixel clock is doubled to be 100 MHz, the energy efficiency of this design would become the best.